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Feb 04, 2017  2. “Double data rate synchronous dynamic random-access memory” (DDR SDRAM). Its frequency varies from 100MHz to 400MHz. It has 184 pins DIMM. There were also some DDR1 with 433MHz launched for overclockers. It was sold with capacities from 128MB to 1GB. For servers you can also find DDR1 with 2GB per DIMM. DDR compatibility on DDR2 Slot. What i want to know is that when i upgrade my motherboard will my current ram be compatible on the DDR2 Slot. (check the motherboard description for details).

184-pin DDR DIMMs use two notches on each side to enable compatibility with both low- and highprofile latched sockets. Note that the key position is offset with respect to the center of the DIMM to prevent inserting it backward in the socket. Jul 02, 2007  I've done some googling about this, but the only answers I've found are that DDR2 has 240 pins and DDR1 has 184 pins, so it wouldn't physically fit. However, my laptop takes 200-pin SO-DIMM DDR ram, and I couldn't help but notice on Newegg that 1GB of 200-pin SO-DIMM DDR2 ram goes for less than half the price of the same amount of DDR1 ram. Jan 23, 2011 204-pin are usually memory for server motherboards, or special boards from DELL, IBM, or Lenovo. If you have a laptop with DDR2 RAM, you MUST buy 200-pin SO-DIMM DDR2 RAM. If you have a desktop with DDR2 RAM, you MUST buy 240-pin DDR2 SDRAM. DDR3 and DDR2 both have the same number of pins, but they do not work in each others slots.

A DIMM or dual in-line memory module comprises a series of dynamic random-access memoryintegrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as IntelP5-based Pentium processors began to gain market share.

While the contacts on SIMMs on both sides are redundant, DIMMs have separate electrical contacts on each side of the module. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium, many processors have a 64-bit bus width, requiring SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this disadvantage.

Variants[edit]

Variants of DIMM slots support DDR, DDR2, DDR3 and DDR4 RAM.

Common types of DIMMs include the following:

Ddr1 Ram Slot Pin Details Download

70 to 200 pins

• 72-pin SO-DIMM (not the same as a 72-pin SIMM), used for FPM DRAM and EDO DRAM
• 100-pin DIMM, used for printer SDRAM
• 144-pin SO-DIMM, used for SDR SDRAM (less frequently for DDR2 SDRAM)
• 168-pin DIMM, used for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers, may be 3.3 or 5 V)
• 172-pin MicroDIMM, used for DDR SDRAM
• 184-pin DIMM, used for DDR SDRAM
• 200-pin SO-DIMM, used for DDR SDRAM and DDR2 SDRAM
• 200-pin DIMM, used for FPM/EDO DRAM in some Sun workstations and servers.

201 to 300 pins

• 204-pin SO-DIMM, used for DDR3 SDRAM
• 214-pin MicroDIMM, used for DDR2 SDRAM
• 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM
• 244-pin MiniDIMM, used for DDR2 SDRAM
• 260-pin SO-DIMM, used for DDR4 SDRAM
• 260-pin SO-DIMM, with different notch position than on DDR4 SO-DIMMs, used for UniDIMMs that can carry either DDR3 or DDR4 SDRAM
• 278-pin DIMM, used for HP high density SDRAM.
• 288-pin DIMM, used for DDR4 SDRAM

168-pin SDRAM[edit]

On the bottom edge of 168-pin DIMMs there are two notches, and the location of each notch determines a particular feature of the module. The first notch is the DRAM key position, which represents RFU (reserved future use), registered, and unbuffered DIMM types (left, middle and right position, respectively). The second notch is the voltage key position, which represents 5.0 V, 3.3 V, and RFU DIMM types (order is the same as above).

DDR DIMMs[edit]

DDR, DDR2, DDR3 and DDR4 all have different pin counts, and different notch positions. As of August, 2014, DDR4 SDRAM is a modern emerging type of dynamic random access memory (DRAM) with a high-bandwidth ('double data rate') interface, and has been in use since 2013. It is the higher-speed successor to DDR, DDR2 and DDR3. DDR4 SDRAM is neither forward nor backward compatible with any earlier type of random access memory (RAM) because of different signalling voltages, timings, as well as other differing factors between the technologies and their implementation.

SPD EEPROM[edit]

A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).^[1]

Error correction[edit]

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips.

Ranking[edit]

Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Ranks that share the same slot, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. The other ranks on the module are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.

After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of the next cell. By interleaving the memory (e.g. cells 0, 4, 8, etc. are stored together in one rank), sequential memory accesses can be performed more rapidly because sense amplifiers have 3 cycles of idle time for recharging, between accesses.

DIMMs are often referred to as 'single-sided' or 'double-sided' to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.

JEDEC decided that the terms 'dual-sided', 'double-sided', or 'dual-banked' were not correct when applied to registered DIMMs (RDIMMs).

Organization[edit]

Most DIMMs are built using '×4' ('by four') or '×8' ('by eight') memory chips with nine chips per side; '×4' and '×8' refer to the data width of the DRAM chips in bits.

In the case of '×4' registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. Como se calcula odds poker table. For '×8' registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted.

Speeds[edit]

For various technologies, there are certain bus and device clock frequencies that are standardized; there is also a decided nomenclature for each of these speeds for each type.

DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs.

Form factors[edit]

Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights. When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a 'low profile' (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform.

With the advent of blade servers, angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of around 0.72 inches (18 mm). The DDR3 JEDEC standard for VLP DIMM height is around 0.740 inches (18.8 mm). These will fit vertically in ATCA systems.

Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around 1.18 inches (30 mm) by standards set by JEDEC. These form factors include 240-pin DIMM, SODIMM, Mini-DIMM and Micro-DIMM.^[2]

Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at 1.23 inches (31 mm). Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly 0.74 inches (19 mm).^[3]

As of Q2 2017, Asus has had a PCI-E based 'DIMM.2', which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support other than Asus.^{[citation needed]}

See also[edit]

• Dual in-line package (DIP)
• Memory geometry – logical configuration of RAM modules (channels, ranks, banks, etc.)
• NVDIMM – non-volatile DIMM
• Rambus in-line memory module (RIMM)
• Single in-line memory module (SIMM)
• Single in-line package (SIP)
• Zig-zag in-line package (ZIP)

References[edit]

1. ^Temperature Sensor in DIMM memory modules
2. ^JEDEC MO-269J Whitepaper., accessed Aug. 20, 2014.
3. ^JEDEC MO-309E Whitepaper., accessed Aug. 20, 2014.

External links[edit]

Double Data Rate Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR SDRAM, is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM. None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, and DDR4 memory modules will not work in DDR1-equipped motherboards, and vice versa.

Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy.^[4][5] The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to double data bus bandwidth without a corresponding increase in clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name 'double data rate' refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate (in bytes/s) of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

• 2Specification
  • 2.2Chip characteristics
• 3Generations

History[edit]

Samsung demonstrated the first DDR memory prototype in 1997,^[1] and released the first commercial DDR SDRAM chip (64Mb) in June 1998,^[6][2][3] followed soon after by Hyundai Electronics (now SK Hynix) the same year.^[7] The development of DDR began in 1996, before its specification was finalized by JEDEC in June 2000 (JESD79).^[8] JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM was released in August 2000.^[9]

Specification[edit]

Modules[edit]

To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with the common address lines are called a memory rank. The term was introduced to avoid confusion with chip internal rows and banks. A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The chip select signal is used to issue commands to specific rank.

Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multi-channel architecture.

Note: All above listed are specified by JEDEC as JESD79F.^[11] All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using tighter-tolerance or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM modules. Modules are instead designed to run at different clock frequencies: for example, a PC-1600 module is designed to run at , and a PC-2100 is designed to run at . A module's clock speed designates the data rate at which it is guaranteed to perform, hence it is guaranteed to run at lower (underclocking) and can possibly run at higher (overclocking) clock rates than those for which it was made.^[12]

DDR SDRAM modules for desktop computers, dual in-line memory modules (DIMMs), have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. Most DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V.

JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40 nominates 3.3V for the right notch position. The orientation of the module for determining the key notch position is with 52 contact positions to the left and 40 contact positions to the right.

Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage.

Capacity

Number of DRAM devices

The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximal number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.

ECC vs non-ECC

Modules that have error-correcting code are labeled as ECC. Modules without error correcting code are labeled non-ECC.

Timings

CAS latency (CL), clock cycle time (t_CK), row cycle time (t_RC), refresh row cycle time (t_RFC), row active time (t_RAS).

Buffering

registered (or buffered) vs unbuffered.

Packaging

Typically DIMM or SO-DIMM.

Power consumption

A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the order of 1–3 W per 512 MB module; this increases with clock rate and when in use rather than idling.^[13] A manufacturer has produced calculators to estimate the power used by various types of RAM.^[14]

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity and the number of chips. ECC modules multiply it by 8/9 because they use 1 bit per byte (8 bits) for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip and number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently, a module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks.

This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single- or dual-ranked.

There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it's unlikely such a module was ever produced.

Chip characteristics[edit]

DRAM density

Size of the chip is measured in megabits. Most motherboards recognize only 1 GB modules if they contain 64M×8 chips (low density). If 128M×4 (high density) 1 GB modules are used, they most likely will not work. The JEDEC standard allows 128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.^{[15][verification needed]}

Organization

The notation like 64M×4 means that the memory matrix has 64 million (the product of banks x rows x columns) 4-bit storage locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC in server environments, while the ×8 and ×16 chips are somewhat less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank.

Double data rate (DDR) SDRAM specification[edit]

Ddr1 Ram Slot Pin Details Price

From Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.

Standard No. 79 Revision Log:

• Release 1, June 2000
• Release 2, May 2002
• Release C, March 2003 – JEDEC Standard No. 79C.^[16]

'This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well.'

Organization[edit]

PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with 16 512 Mbit chips, 8 on each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized as 2²⁶ 8-bit words, commonly expressed as 64M×8. Memory manufactured in this way is low-density RAM and is usually compatible with any motherboard specifying PC3200 DDR-400 memory.^{[17][citation needed]}

High-density RAM[edit]

In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low-density from high-density RAM. High-density DDR RAM modules will, like their low-density counterparts, usually be double-sided with eight 512 Mbit chips per side. The difference is that each chip, instead of being organized as 64M×8, is organized as 2²⁷ 4-bit words, or 128M×4.

High-density memory modules are assembled using chips from multiple manufacturers. These chips come in both the familiar 22 × 10 mm (approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA package sizes. High-density chips can be identified by the numbers on each chip.

High-density RAM devices were designed to be used in registered memory modules for servers. JEDEC standards do not apply to high-density DDR RAM in desktop implementations.^{[citation needed]} JEDEC's technical documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 being classified as high-density^[clarify]. As such, high density is a relative term, which can be used to describe memory that is not supported by a particular motherboard's memory controller.^{[citation needed]}

Generations[edit]

DDR (DDR1) was superseded by DDR2 SDRAM, which had modifications for higher clock frequency and again doubled throughput, but operates on the same principle as DDR. Competing with DDR2 was RambusXDR DRAM. DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by DDR3 SDRAM, which offered higher performance for increased bus speeds and new features. DDR3 has been superseded by DDR4 SDRAM, which was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes.

DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although the effective clock rates of DDR2 are higher than DDR, the overall performance was not greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.^[18]

Memory manufacturers stated that it was impractical to mass-produce DDR1 memory with effective transfer rates in excess of 400 MHz (i.e. 400 MT/s and 200 MHz external clock) due to internal speed limitations. DDR2 picks up where DDR1 leaves off, utilizing internal clock rates similar to DDR1, but is available at effective transfer rates of 400 MHz and higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates by again doubling the prefetch depth.

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as 16 banks, 4 bank groups with 4banks for each bank group for x4/x8 and 8 banks, 2 bank groups with 4 banks for each bank group for x16 DRAM.The DDR4 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined withan interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAMconsists of a single 8n-bit-wide 4-clock data transfer at the internal DRAM core and 8 corresponding n-bit-wide half-clock-cycle data transfers at the I/O pins.^[19]

RDRAM was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from their chipsets. DDR1 memory's prices substantially increased since Q2 2008, while DDR2 prices declined. In January 2009, 1 GB DDR1 was 2–3 times more expensive than 1 GB DDR2. High-density DDR RAM suit about 10% of PC motherboards on the market, while low-density suit almost all motherboards on the PC Desktop market.^{[citation needed]}

Mobile DDR[edit]

MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. Through techniques including reduced voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency.

See also[edit]

References[edit]

1. ^ ^ab'Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review'. TechPowerUp. March 8, 2012. Retrieved 25 June 2019.
2. ^ ^ab'Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs'. Samsung Electronics. Samsung. 17 September 1998. Retrieved 23 June 2019.
3. ^ ^ab'Samsung Demonstrates World's First DDR 3 Memory Prototype'. Phys.org. 17 February 2005. Retrieved 23 June 2019.
4. ^Northwest Logic DDR Phy datasheetArchived 2008-08-21 at the Wayback Machine
5. ^'Memory Interfaces Data Capture Using Direct Clocking Technique (Xilinx application note)'(PDF). xilinx.com.
6. ^'Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option'. Samsung Electronics. Samsung. 10 February 1999. Retrieved 23 June 2019.
7. ^'History: 1990s'. SK Hynix. Retrieved 6 July 2019.
8. ^'The Love/Hate Relationship with DDR SDRAM Controllers'.
9. ^'Iwill Reveals First DDR Motherboard - PCStats.com'. www.pcstats.com. Retrieved 2019-09-09.
10. ^Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100 MHz) = 10 ns per clock cycle.
11. ^'DOUBLE DATA RATE (DDR) SDRAM STANDARD - JEDEC'. www.jedec.org.
12. ^'What is the difference between PC-2100 (DDR-266), PC-2700 (DDR-333), and PC-3200 (DDR-400)?'. Micron Technology, Inc. Archived from the original on 2013-12-03. Retrieved 2009-06-01.
13. ^Mike Chin: Power Distribution within Six PCs.
14. ^Micron: System Power CalculatorsArchived 2016-01-26 at the Wayback Machine
15. ^'Low Density vs High Density memory modules'. ebay.com.
16. ^http://www.jedec.org/download/search/JESD79F.pdf DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION (Release F)
17. ^'Per bytes RAM memory access'. Super User. Retrieved 2018-10-21.
18. ^DDR2 vs. DDR: Revenge GainedArchived 2006-11-21 at the Wayback Machine
19. ^'DDR4 SDRAM Standard JESD79-4B'.

External links[edit]

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